FIG. 3A illustrates a basic picture of a computing system which includes a Central Processing Module 10, an Input/Output Module or Modules 50, and a Main System Memory Module 40 all interconnected by dual redundant system busses 22a and 22b. This configuration might be considered typical of a general computer system.
FIG. 3B is an illustration of the Central Processing Module (CPM) pathway with a cache memory module 19 added in order to enhance system performance. Whenever the processor 14 needs data from main memory 40, the cache memory unit 19 is the first line of resource for this data. An efficient cache design will, on average, contain the requested processor information about 90% of the time. If the cache memory 19 does not have the required information in its latest, most valid state, then the data must be accessed from the system Main Memory 40 over some system bus mechanism such as the processor bus 14b and the dual redundant system busses 22a, 22b. In this latter situation requiring main memory access, this, of course, involves a longer period of time and thus slows down the processor operation than if the processor were able to immediately retrieve the requested data from the cache memory 19 via the processor bus 14b.
FIG. 3C shows the elements of the Central Processing Module 10 in greater detail. Here, the processor 14 connects to the processor bus 14b, while the processor 14 itself has its own first level cache 19c1, but then can also access, via processor bus 14b, the second level cache module 19c2. The processor bus 14b also connects through a unit designated the Data Path Array 20, if there is a requirement for access to the system busses over to main memory. Here, the cache memory module 19 of FIG. 3B is illustrated as two separate units. The first unit designated the first level cache 19c1 is shown internally to the processor 14. The second level cache module 19c2 is shown connected to the processor bus 14b.
In order to gain higher system performance, multi or double-levels of cache are often used. When the processor 14 needs memory data, the first level cache 19c1 is the first resource that the processor 14 will seek. If the first level cache 19c1 does not have the information requested, then the processor will access the second level cache 19c2 to try to see if the requested data is available. Finally, if neither one of the cache units have the data needed, then of course, a much slower cycle of action is required for the processor to access main system memory in order to get the required data. Typically, the first level cache unit 19c1 is quite small and may even be integrated into a processing chip. Then typically, the second level cache 19c2 is larger in storage capacity and will be often external to the processor unit 14 as indicated in FIG. 3C.
Also seen in FIG. 3C is a unit called the "Snoop Logic 23s". This logic monitors both system busses 22a and 22b for any operation that may modify data in any one of the memory locations, that is to say, this is typical of write-type operations. The snoop block 23s captures the address values for all of these system bus operations (writes), queues them up, and passes them on to the second level cache 19c2 at a convenient time for subsequent use or investigation. The snooping (or spying) function is necessary to assure data coherency in the cache structures. When the cache investigates each of the addresses that have been queued within it, it checks the cache tag unit to see if the cache currently contains a valid version of that particular memory address. If it does not contain a valid version, then that particular queued address is discarded. If the cache unit does contain a copy of the queued address, then the cache will operate an "invalidation" operation where it marks, in its cache tag unit, that locational address as "invalid".
With the multiple levels (2 levels) of cache structures as shown in FIG. 3C, there is an additional complication in regard to the "invalidation cycle process" which is added. In this case, it is necessary for the first level cache tag unit in 19c1 to also investigate each of the queued spy address values as well as the second level cache 19c2. This necessitates the transfer of all queued address values on the processor bus 14b up to and over to the processor first level cache 19c1. Thus, this requires and becomes a significant amount of extra traffic on the processor bus 14b. When the processor bus 14b is busy carrying an invalidation address, the processor 14 cannot use the bus for its real processing operations. The present system and method presents a method to reduce the processor bus traffic on bus 14b, due to invalidations, and thus to increase the amount of work that the processor can get done and increase its efficiency.
FIG. 3D is an expanded view of the second level cache memory, 19c2, design to show the operative elements of a cache memory module. The processor bus 14b is made of two subordinate busses indicated as the address bus 14ba and the data bus 14bd. The cache module is shown operatively as having three major block units. These units include a Tag RAM 19ta, a Data RAM unit 19da, and a Cache Control block unit 16cc. The Cache Control unit 16cc is actually a part of the programmable array logic, Control PAL 16 which was previously seen in FIG. 3C. The Tag RAM block in all cache designs, holds the addresses, (indexes) of the data contained within the cache at any particular moment. The Tag addresses in 19ta provide the means by which comparisons of requested processor address values can be made with the held address values in the Tag RAM 19ta. When a match occurs, this is called a cache "hit", because it indicates that the cache does indeed contain valid data for that particular specified address.
The Data RAM block 19da is the storage area for all of the data held within the cache module at any particular moment. These type of Data RAMs are generally expansive and very fast operating devices which can return data to the processor on "cache hit" conditions. The Cache Control block unit 16cc, is used to monitor the Tag RAM "hit" condition, and further controls the reading out of the Data RAMs 19da. When a Tag "miss" condition occurs (i.e., not a "hit"), then this Cache Control block controls the writing into the Data RAMS 19da of any data received subsequently from the main memory 40.